The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly to a method of manufacturing a TFT array substrate of an active matrix liquid crystal display.
In a liquid crystal display, an electro-optic characteristic of a liquid crystal is utilized and combined with a polarizing plate in order to carry out display by controlling a voltage to be applied to the liquid crystal. A liquid crystal display has a light weight than that of a CRT and is excellent in portability, so that has been applied to a display device of a mobile computer in recent years.
In particular, an active matrix liquid crystal display, in which a switching element such as a thin film transistor (TFT) is provided for each pixel to control a voltage to be applied to a liquid crystal, is characterized by a higher display quality as compared with a simple matrix type liquid crystal display, and has vigorously been developed and applied.
FIG. 1 shows an equivalent circuit of a basic active matrix type liquid crystal display, and an operation thereof will be described. FIG. 1(b) is a partially enlarged view showing a P portion of FIG. 1(a).
A switching element 7 such as a TFT, a liquid crystal capacitance (capacitance of liquid crystal in the pixel) 8 and an auxiliary capacitance 9 are formed to define a pixel in the intersecting portion of a gate line 1 and a source line 2. The pixels are arranged in a matrix to form a TFT array substrate.
When a selection pulse is applied to the gate line, all of the switching elements connected to the gate line are turned ON and a signal applied to a source line connected to each switching element is written to the liquid crystal capacitance and the auxiliary capacitance through the switching element. When the application of the selection pulse is completed and the gate line is brought into a non-selection state, the switching elements are turned OFF so that electric charges written to the liquid crystal capacitance and the auxiliary capacitance are held until one vertical scanning period passes and the selection pulse is applied again to the gate line.
In the active matrix type liquid crystal display, usually, a switching element such as a TFT is provided on one of two substrates to form a TFT array substrate, a common electrode is provided on the other substrate to form a counter substrate, and the two substrates are opposed to each other interposing a liquid crystal layer therebetween.
A method for manufacturing a TFT array substrate according to the conventional art will be described with reference to FIGS. 2, 3 and 4.
FIG. 2 is an enlarged plane view showing the main part of the TFT array substrate. In FIG. 2, a TFT comprising a gate electrode 12, a source electrode 21 and a drain electrode 22 is formed in the intersecting portion of a gate line 13 and a source line 20, and the drain electrode 22 of the TFT is connected to a pixel electrode 27 through a contact hole 24. In order to apply a selection pulse from the outside, the end of the gate line 13 is extended to the outside of a display region of the liquid crystal display to form a lower pad 15. The lower pad 15 is connected to an upper pad 28 through a contact hole 25, and the selection pulse is inputted from the upper pad.
The end of the gate line 20 is also extended to the outside of the display region of the liquid crystal display to form a lower pad 23, which is not shown in FIG. 2. The lower pad 23 is connected to an upper pad 29 through a contact hole 26, and a signal is inputted from the upper pad.
The reference numeral 14 in FIG. 2 denotes a common line for forming an auxiliary capacitance together with a pixel electrode 27. Moreover, the reference numeral 38 denotes a channel of the TFT.
FIGS. 3 and 4 are sectional views illustrating the method for manufacturing a TFT array substrate in FIG. 2.
First of all, a first metal layer is formed on an insulating substrate 11 by using a method such as sputtering. The first metal layer comprises metal such as Cr, Al or Mo, an alloy containing the metal as an essential component, or a laminated layer thereof. Then, photolithography is carried out by using a photoresist, thereby removing an unnecessary portion from the first metal layer by etching or the like. Thus, a gate electrode 12, a gate line 13, a common line 14 and a lower pad 15 are formed. This state is shown in FIG. 3(a).
Next, an insulating film (a gate insulating film) 16 comprising SiNx or SiO2 is formed by various CVD methods such as plasma CVD, or by sputtering, evaporation, coating or the like. Furthermore, an a-Si:H layer (a first semiconductor layer) 17, and a semiconductor layer (an impurity semiconductor layer or a second semiconductor layer) 18 such as an n+a-Si:H film or a microcrystal n+Si layer which is doped with an impurity such as phosphorus, antimony or boron are formed by plasma CVD, sputtering or the like. Furthermore, a second metal layer 19 is formed by using sputtering or the like. A second metal layer comprises metal such as Cr, Al or Mo, an alloy containing the metal as an essential component or a laminated layer thereof.
Subsequently, a photoresist R is applied to form a resist pattern comprising a region A in which the photoresist R has a great thickness, a region B in which the photoresist R has a small thickness, and a region C in which the photoresist R is removed. This state is shown in FIG. 3(b).
Next, the second metal layer 19 is subjected to etching by using the resist pattern. The second metal layer 19 in the region C having no photoresist R is selectively removed. This state is shown in FIG. 3(c).
Then, the photoresist R in the region B is removed. At this time, since the photoresist R in the region A has a great thickness, it is not removed but remained. This state is shown in FIG. 3(d).
Next, the photoresist R remaining in the region A is used to first etch the semiconductor layers 18 and 17, thereby removing the semiconductor layers 18 and 17 in the region C, and to then etch the second metal layer 19, thereby removing the second metal layer 19 in the region B. This state is shown in FIGS. 3(e) and 4(a).
Furthermore, the semiconductor layer 18 in the region B is removed by etching and the whole resist R is then removed. This state is shown in FIG. 4(b). A source line 20, a source electrode 21, a drain electrode 22 and a lower pad 23 are formed on a substrate.
Subsequently, a protective film 35 is formed over the whole surface and photolithography is then carried out by using the photoresist or the like, and contact holes 24, 25 and 26 are formed by etching or the like. This state is shown in FIG. 4(c).
Finally, ITO (Indium Tin Oxide) is formed over the whole surface, the photolithography is carried out by using the photoresist or the like, and an unnecessary portion is removed by etching to form an ITO pixel electrode 27 and upper pads 28 and 29. This state is shown in FIG. 4(d).
According to the manufacturing method described above, a TFT array substrate can be manufactured by carrying out the photolithography four times in total, that is, by means of four photomasks. Therefore, a process can be shortened and a cost can be reduced.
In the above-mentioned manufacturing method, meanwhile, the source line 20, the source electrode 21, the drain electrode 22 and the lower pad 23, and the semiconductor layers 18 and 17 which are positioned thereunder are formed by using the same photoresist R. However, because methods or conditions of the etching are different, an amount of a reduction in the widthwise direction (side etching amount) in the line during the etching of the second metal layer 19 is larger than the side etching amounts of the semiconductor layers 18 and 17. As shown in FIGS. 4(a) to 4(d), therefore, the semiconductor layer 18 and the semiconductor layer 17 are protruded beside the source line 20.
In general, in the case in which the material of the source line (i.e. the second metal layer 19) is Cr, Al, Mo or the like, the side etching amount is approximately 0.5 to 1.0 xcexcm on either side. On the other hand, the side etching amounts of the semiconductor layer 18 and the semiconductor layer 17 are approximately 0 xcexcm. Accordingly, in the case in which the width of the source line in the photomask to be used in the photolithography is 10 xcexcm, a source line to be actually formed has a width of 8 to 9 xcexcm and the semiconductor layer 18 and the semiconductor layer 17 are protruded by approximately 1 to 2 xcexcm.
In order to obtain a liquid crystal display in which display having a high luminance can be carried out and a display quality is excellent, it is desirable that the aperture ratio of a TFT array substrate should be increased as much as possible. In order to prevent the delay of a signal to be applied to the source line 20 and a degredation in a display quality such as an uneven luminance, moreover, it is desirable that the resistance of the source line 20 should be reduced as much as possible.
If the protrusion of the semiconductor layer 18 and the semiconductor layer 17 can be removed, the aperture ratio can be enhanced without decreasing the width of the source line 20, that is, without increasing the resistance of the source line 20. In addition, if the aperture ratio is equal, the width of the source line 20 can be more increased so that the resistance of the source line 20 can be reduced.
Furthermore, there is also a problem in that the semiconductor layers 18 and 17 thus protruded form a capacitance together with the common electrode of the counter substrate, thereby increasing a source-common capacitance.
In the method of manufacturing a TFT array substrate using four photomasks described above, particularly, the second metal layer 19 (the source line 20) is exposed to the etching plural times (see FIG. 3(c) and FIG. 4(a)).
For this reason, the difference between the side etching amount of the source line 20 and the side etching amounts of the semiconductor layers 18 and 17 is further increased. For example, in the case in which the source line in the photomask has a width 10 xcexcm, a source line to be actually formed has a width of approximately 6 to 7 xcexcm and the semiconductor layers 18 and 17 are protruded by approximately 3 to 4 xcexcm.
Accordingly, a reduction in the aperture ratio, an increase in the resistance of the source line and an increase in the source-common capacitance have become more serious. Therefore, there has been greatly desired a manufacturing method capable of removing the protruded semiconductor layers 18 and 17.
It is an object of the present invention to remove a semiconductor layer protruded beside a source line in a process for manufacturing a TFT array of an active matrix liquid crystal display device.
According to the present invention, a gate line, a source line, a TFT element and the like are formed; thereafter a passivation film is then formed; and the passivation film on the source line, the passivation film provided beside the source line and a gate insulating film provided beside the source line are simultaneously removed to expose the source line and a semiconductor layer provided under the source line when removing a part of the passivation film to form a contact hole.
Furthermore, a portion in the exposed semiconductor layer which is protruded besides the source line is removed by using, as a mask, a resist pattern for removing a part of the passivation film and/or a source line.
Alternatively, a portion in the exposed semiconductor layer which is protruded beside the source line is removed by using, as a mask, the passivation film from which a part thereof is removed and/or the source line.
According to another aspect of the present invention, a gate line, a source line, a TFT element and the like are formed and a passivation film is not then formed, and a portion in a semiconductor layer provided under the exposed source line which is protruded beside the source line is removed by using the source line as a mask.
According to still another aspect of the present invention, a semiconductor layer is caused to remain beside the source line when forming the source line. Consequently, when removing a part of the passivation film to form a contact hole, only the passivation film provided on and beside the source line is removed and a gate insulating film provided beside the source line is not removed.
Furthermore, a portion in the semiconductor layer exposed by the removal of the passivation film which is protruded beside the source line is removed by using, as a mask, a resist pattern for removing a part of the passivation film and/or the source line.
Alternatively, a portion in the semiconductor layer exposed by the removal of the passivation film which is protruded beside the source line is removed by using, as a mask, the passivation film from which a part thereof is removed and/or the source line.
In the present invention, when selectively removing a part of an ITO film, the ITO film provided on the source line is not removed but may be left to cover the source line.